1. Field of the Invention
The present invention relates to a flash memory allocating method, and more particularly, to an allocating method for prolonging the lifetime of a NAND flash memory.
2. Description of the Prior Art
The non-volatile NAND flash memory is one of the most popular storage devices in the field of portable electronic devices or embedded electronic systems. For example, a personal digital assistant (PDA), a digital camera, an MP3 walkman, and a recorder device are all installed with a NAND flash memory. The greater the number of times the NAND flash memory is accessed, the more inaccurate the data stored in the NAND flash memory will be. The conventional way to solve the above-mentioned problem is to utilize an error codes correction (ECC) configuration in the NAND flash memory to recover the error data. For example, in the conventional NAND flash memory having a page size of 2 K bits, there is always a spare area of 64 bytes for storing the parity code generated by a specific ECC algorithm when the specific ECC algorithm performs an ECC calculation upon the data of the page, and in the conventional NAND flash memory having a page size of 4 K bits, there is always a spare area of 218 bytes for storing the parity code generated by the specific ECC algorithm when the specific ECC algorithm performs the ECC calculation upon the data of the page.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating an allocating method of a spare area in each page of a conventional NAND flash memory, wherein the specific ECC algorithm utilizes a Reed-Solomon ECC algorithm and a Bose, Chaudhuri and Hocquengham (BCH) ECC algorithm. When a BCH 8 ECC algorithm encodes the data in the NAND flash memory, the parity code generated in the encoding process may occupy 13 bytes of the spare area in each page. When a Reed-Solomon 6 ECC algorithm encodes the data in the NAND flash memory, the parity code generated in the encoding process may occupy 15 bytes of the spare area in each page. When a Reed-Solomon 8 ECC algorithm encodes the data in the NAND flash memory, the parity code generated in the encoding process may occupy 20 bytes of the spare area in each page. When a Reed-Solomon 10 or a BCH 15 ECC algorithm encodes the data in the NAND flash memory, the parity code generated in the encoding process may occupy 25 bytes of the spare area in each page. When the conventional NAND flash memory is encoded/decoded by the Reed-Solomon ECC algorithm or the BCH ECC algorithm, 512 bytes of data storage capacity is allocated in each page. Therefore, when the conventional NAND flash memory is encoded/decoded by the Reed-Solomon ECC algorithm or the BCH ECC algorithm, the ability to correct the error data in the NAND flash memory is limited by the size of the spare area in each page. In other words, the reason that the Reed-Solomon ECC algorithm and the BCH ECC algorithm cannot provide a much better error correcting ability upon the NAND flash memory is due to the predetermined size of the spare area in each page, which is an inconvenient restriction for a user who requires frequent access of the NAND flash memory.